1. Field of the Invention
Example embodiments of the present invention relates in general to a semiconductor chip package and a method of fabricating the same, and more particularly to a multi-stack package (MSP) that may include a stack of semiconductor chips, and a method of fabricating the same.
2. Description of the Related Art
One way to increase capacitance of a semiconductor product may be to increase a packing density in a unit semiconductor device. This may involve a design rule decrease, that may result in expensive and time-consuming microscopic pattern techniques.
Another way to increase capacitance of a semiconductor product may be to implement MSP techniques. MSP techniques may involve stacking a plurality of unit semiconductor devices to form a single package. Conventional integration of a semiconductor device may be regarded as an increase of the packing density within a two-dimensional area, while MSP integration may be regarded as an increase of the packing density within a three-dimensional space by virtue of the semiconductor devices being stacked.
An MSP may be embodied in several ways. For example, unit chip packages may be stacked and electrically interconnected via a multi-step wire bonding process. As another example, which may be known as a ball grid array (BGA) type MSP, conductive solder bumps may be used to electrically interconnect and stack unit chip packages. BGA type MSPs may be fabricated without performing the multi-step wire bonding process.
A wire bonding BGA type MSP (wBGA), which may expose semiconductor chips, may be a recent focus in the BGA type multi-stack package technologies. However, the wBGA type MSP may not sufficiently protect the exposed semiconductor chips.
FIGS. 1A and 1B are sectional views of a conventional wBGA type MSP.
Referring to FIG. 1A, the conventional MSP 100 may have a structure in which a plurality of unit chip packages 140a, 140b, 140c and 140d are stacked.
Referring to FIG. 1B, the uppermost Unit chip package 140d may have a semiconductor chip 130d bonded on a printed circuit board (PCB) 110d by an adhesive 135d. The semiconductor chip 130d may be connected to the PCB 110d via a conductive wire 115d, and a solder bump 125d may be disposed on a surface of the PCB 110d as a connection terminal. The PCB 110d may include a board core 106d and photo solder resist layers 104d and 108d may be provided on opposite surfaces of the board core 106d. The wire 115d may be coated with an encapsulation layer 120d. 
The unit chip packages 140a, 140b, 140c and 140d of FIG. 1A may have a structure similar to the unit chip package 140d shown in FIG. 1B. A metal plate 150 may be bonded to the semiconductor chip 130d of the uppermost unit chip package 140d of FIG. 1A by an adhesive 155. The metal plate 150 may protect the semiconductor chip 130d from the external environment.
Although the conventional metal plate 150 may be thought of as generally providing acceptable performance, it is not without shortcomings. For example, separate equipment may be necessary for mounting the metal plate 150 on the MSP 100. Also, the metal plate 150 may be fabricated from a material different from the lower unit chip packages 140a, 140b, 140c and 140d. 
Furthermore, the uppermost unit chip package 140d may be bent due to bending of the metal plate 150 that may occur when the MSP 100 is module-mounted. In some cases, such bending may cause portions of the MSP 100 to become inadvertently separated. Moreover, the metal plate 150 may make the MSP 100 more cumbersome and heavy so that the MSP 100 may be more easily dropped during secondary module mounting.